The present invention relates to signal receivers at inputs of integrated circuits for receiving high-frequency signals thereon. More specifically, the present invention relates to improvements in matching impedances.
Impedance matching is the process of matching impedances between a driver and a receiver. At high frequencies, having matched impedances is important to reduce the amount of signal reflection that occurs at the receiver.
As signal rates increase in integrated circuits (chips), suitably matching impedances between a driver and receivers becomes more problematic. The ideal driver/receiver combination would be a Thevenin equivalent source pulse generator with the output impedance of the driver matching the transmission line impedance (Z0) of the line between the driver and the receiver and matching the input impedance of the receiver.
One solution to input impedance matching is shown in FIG. 1. This solution is often used with CMOS technology chips and where impedance matching is critical to obtaining maximum data transfer rates. As shown in FIG. 1, external resistors 10, 12 are used to match the input impedance of input 14 to the chip. Those external resistors 10, 12 can be discrete resistors added to the printed circuit board on which the chip is to be mounted, or the resistors might be fabricated into the package that supports the chip and makes the electrical connections of the chip available to the traces of the printed circuit board. Either of those solutions works well, but requires additional effort and expense to separately mount those extra components and may decrease the reliability of the circuit due to added connections on the printed circuit board. An additional complexity is introduced by the fact that the resistive components are separate and subject to poor thermal control.
Thus, controlling receiver input resistance at the chip level would benefit chip-to-chip communications. FIG. 2 illustrates one on-chip solution to controlling receiver input resistance. There, two PMOS elements 20, 22 are coupled in parallel such that the parallel resistance of those PMOS elements is at the proper value as set by a control input. An analogous NMOS circuit might also be used. In this approach, the transistors are used to mimic a linear termination but faster response is sometimes needed.
In an input receiver circuit according to one embodiment of the present invention, the circuit includes a signal input for receiving a signal input to a chip, a chip output for supplying a buffered signal to circuitry on the chip and a positive feedback circuit coupled between the chip output and the signal input. In one embodiment, the positive feedback circuit comprises a first inverter having an input coupled to the signal input, a second inverter having an input coupled to an output of the first inverter, wherein an output of the second inverter provides the chip output, and an inverting buffer having an input coupled to the output of the second inverter and an output coupled to the signal input.
One advantage of such an input receiver circuit is that it provides preemphasis to open up the xe2x80x9ceyexe2x80x9d in a sampling graph, and it does so without increasing latency.